This invention relates to instruction ordering for in-progress operations.
Many computing systems utilize virtual memory systems to allow programmers to access memory addresses without having to account for where the memory addresses reside in the physical memory hierarchies of the computing systems. To do so, virtual memory systems maintain a mapping of virtual memory addresses, which are used by the programmer, to physical memory addresses that store the actual data referenced by the virtual memory addresses. The physical memory addresses can reside in any type of storage device (e.g., SRAM, DRAM, magnetic disk, etc.).
When a program accesses a virtual memory address, the virtual memory system performs an address translation to determine which physical memory address is referenced by the virtual memory address. The data stored at the determined physical memory address is read from the physical memory address, as an offset within a memory page, and returned for use by the program. The virtual-to-physical address mappings are stored in a “page table.” In some cases, the virtual memory address be located in a page of a large virtual address space that translates to a page of physical memory that is not currently resident in main memory (i.e., a page fault), so that page is then copied into main memory.
Modern computing systems include one or more translation lookaside buffers (TLBs) which are caches for the page table, used by the virtual memory system to improve the speed of virtual to physical memory address translation. Very generally, a TLB includes a number of entries from the page table, each entry including a mapping from a virtual address to a physical address. Each TLB entry could directly cache a page table entry or combine several entries in the page table in such a way that it produces a translation from a virtual address to a physical address. In general, the entries of the TLB cover only a portion of the total memory available to the computing system. In some examples, the entries of the TLB are maintained such that the portion of the total available memory covered by the TLB includes the most recently accessed, most commonly accessed, or most likely to be accessed portion of the total available memory. In general, the entries of a TLB need to be managed whenever the virtual memory system changes the mappings between virtual memory addresses and physical memory addresses. This management may affect any operations that are in-progress from instructions that reference virtual memory address. In some systems, any instructions with in-progress operations are allowed to complete before a virtual memory address referenced by those instructions is invalidated.